The present invention relates, in general, to error detection and correction and, more particularly, to error detection and correction using memory multiplexers (MEMMUXs).
Currently, memory is commonly arranged in a series of logical banks. In the present application, the memory referred to is generally a Random Access Memory (RAM) and is typically a Dynamic Random Access Memory (DRAM). Each memory device typically comprises a 4-bit output and is referred to as a 4.times. DRAM. For example, in a 32-bit system, a set of eight 4-bit DRAMs would be used. A 32-bit word would have the first four bits of the word stored in one DRAM; the next four bits in the next DRAM; and so on until the entire word was stored.
When the word is read from memory, it will often be loaded into an Error Detection And Correction (EDAC) (such as the MC74F2960 Error Detection and Correction Circuit of Motorola Inc.) device so that the integrity of the word can be determined before being transfered. To accomplish the error detection and correction of the data word, an error correction word is transfered with the data word to the EDAC. For a 32-bit word, the error correction word is a 7-bit word. In a 64-bit system, the error correction word would be an 8-bit word.
An EDAC is able to detect one and two bit errors and can correct one bit errors. The corrected word is then forwarded to the system.
However, a problem exists in the event one of the DRAMs goes bad. This would automatically cause 4-bits of the 32-bit word to be suspect. Since the EDAC can neither detect or correct a 4-bit error, this would pass through undetected.